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[arch/x86] Intel APX support#6423

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emesare merged 4 commits intoVector35:devfrom
nullableVoidPtr:dev
Feb 24, 2026
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[arch/x86] Intel APX support#6423
emesare merged 4 commits intoVector35:devfrom
nullableVoidPtr:dev

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@nullableVoidPtr nullableVoidPtr commented Feb 17, 2025

  • EGPRs
  • JMPABS
  • Push/Pop
    • PUSH2
    • PUSHP
    • POP2
    • POPP
  • CCMPSCC
  • CFCMOVCC
  • CTESTSCC
  • SETCC
  • Zero Upper
    • IMUL
    • SETCC
  • New Data Destination

Resolves #5246

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@nullableVoidPtr thx for your work! Please let me know when you think the code is ready for reviewer!

@galenbwill galenbwill self-assigned this May 7, 2025
@galenbwill galenbwill added Arch: x86 Issues with the x86/x64 architecture plugin Type: Enhancement Component: Architecture Issue needs changes to an architecture plugin Impact: Low Issue is a papercut or has a good, supported workaround Effort: Medium Issues require < 1 month of work State: Blocked (Customer) Issue is blocked on waiting for a response from a customer labels May 7, 2025
@galenbwill galenbwill added this to the Future milestone May 7, 2025
@galenbwill galenbwill changed the title [arch/x86] Intel APX support [arch/x86] [WIP] Intel APX support May 7, 2025
@galenbwill galenbwill removed their assignment Aug 6, 2025
@psifertex psifertex marked this pull request as draft October 23, 2025 20:20
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emesare commented Dec 1, 2025

The push / pop lifting looks fine on the binary https://github.com/user-attachments/files/23866882/apxbin.zip

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emesare commented Dec 1, 2025

image

CCMP also looks correct, the conditional CMP block and the DFV write block look fine.

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Thanks for the test bin - I'll be sure to test against that; do you have a corpus for the other extension instructions?

@nullableVoidPtr nullableVoidPtr marked this pull request as ready for review December 3, 2025 08:50
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stong commented Dec 3, 2025

👏

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emesare commented Dec 3, 2025

Thanks for the test bin - I'll be sure to test against that; do you have a corpus for the other extension instructions?

I do not, I will make another with more of the extensions instructions expressed, thank you for responding quick!

@emesare emesare self-assigned this Dec 3, 2025
@emesare emesare removed the State: Blocked (Customer) Issue is blocked on waiting for a response from a customer label Dec 3, 2025
@emesare emesare modified the milestones: Future, Jotunheim Dec 3, 2025
@nullableVoidPtr nullableVoidPtr changed the title [arch/x86] [WIP] Intel APX support [arch/x86] Intel APX support Dec 4, 2025
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Heya, I consider this extension complete - is there any other blockers besides your testing?

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emesare commented Jan 26, 2026

Heya, I consider this extension complete - is there any other blockers besides your testing?

None, just have not merged it yet, will get it done shortly, sorry!

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emesare commented Feb 23, 2026

The sizing of non-ndd instructions was messed up between commits, I am running tests on the branch below, if you could double check my changes, once im done what I will do is merge my changes into your branch and then squash with you as the author

ab9dd3f

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Good catch with the NDD op lens, LGTM

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emesare commented Feb 24, 2026

Okay testing is done, I checked this branch against ~200k object files and nothing changed (which is good!), no performance regressions either, however I did find a blind spot in our COFF relocations in one binary leading to a fall through of a no-return call that then disassembles as an NDD instruction, but that is a separate issue entirely 😆.

@emesare emesare merged commit 3eda43f into Vector35:dev Feb 24, 2026
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emesare commented Feb 24, 2026

Available in 5.3.9178 thank you!

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Arch: x86 Issues with the x86/x64 architecture plugin Component: Architecture Issue needs changes to an architecture plugin Effort: Medium Issues require < 1 month of work Impact: Low Issue is a papercut or has a good, supported workaround

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Add support for Intel APX

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